Pozzi, Laura Ferretti, Lorenzo 2020-10-30 High Level Synthesis (HLS) is a process which, starting from a high-level description of an application (C/C++), generates the corresponding RTL code describing the hardware implementation of the desired functionality. The HLS process is usually controlled by user-given directives (e.g., directives to set whether or not to unroll a loop) which influence the resulting implementation area and latency. By using HLS, designers are able to rapidly generate different hardware implementations of the same application, without the burden of directly specifying the low level implementation in detail. Nonetheless, the correlation among directives and resulting performance is often difficult to foresee and to quantify, and the high number of available direct- ives leads to an exponential explosion in the number of possible configurations. In addition, sampling the design space involves a time-consuming hardware synthesis, making a brute-force exploration infeasible beyond very simple cases. However, for a given application, only few directive settings result in Pareto- optimal solutions (with respect to metrics such as area, run-time and power), while most are dominated. The design space exploration problem aims at identifying close to Pareto-optimal implementations while synthesising only a small portion of the possible configurations from the design space. In this dissertation I present an overview of the HLS design flow, followed by a discussion about existing strategies in literature. Moreover, I present new exploration methodologies able to automatically generate optimised implementations of hardware accelerators. The proposed approaches are able to retrieve a close approximation of the real Pareto solutions while synthesising only a small fraction of the possible design, either by smartly navigating their design space or by leveraging prior knowledge. Herein, I also present a database of design space explorations whose goal is to help researchers to design new strategies by offering a reliable source of knowledge for machine learning based approaches, and standardise the methodologies evaluation. Lastly, the stepping-stones of a new approach relying on deep learning strategies with graph neural networks is presented, and final remarks about future research directions are discussed. application/pdf https://susi.usi.ch/global/documents/319184 https://n2t.net/ark:/12658/srd1319184 https://susi.usi.ch/documents/319184/files/2020INFO016.pdf eng info:eu-repo/semantics/altIdentifier/urn/urn:nbn:ch:rero-006-118902 info:eu-repo/semantics/altIdentifier/ark/12658/srd1319184 info:eu-repo/semantics/openAccess License undefined Design space exploration High-level synthesis HW/SW co-design Hardware accelerators Heterogeneous architectures Computer architectures info:eu-repo/classification/udc/004 Design space exploration in high-level synthesis http://purl.org/coar/resource_type/c_db06