Pozzi, Laura Ansaloni, Giovanni 2011-05-19 Coarse Grained Reconfigurable Arrays have emerged, in recent years, as promising candidates to realize efficient reconfigurable platforms. CGRAs feature high computational density, flexible routing interconnect and rapid reconfiguration, characteristics that make them well-suited to speed up execution of computational kernels. A number of designs embodying the CGRA concept have been proposed in literature, most of them presenting specific, ad-hoc solutions. This thesis instead takes a more general approach, focusing on techniques that can be adapted to arrays having different architectural features, enabling experimental comparisons and exploration of the design space. At the hardware level, a template virtual prototype, named Expression Grained Reconfigurable Array, is introduced. Instances can be derived from the template at design time, varying the architecture structure as well as the characteristics of its different blocks. Presented design space explorations include the search of an efficient multi-ALU structure to be used as computational cell and exploration of heterogenous elements to support parallel execution of whole kernels. EGRA instances are defined at the RTL level. This feature makes it possible to simulate their behavior employing a digital simulation environment. The thesis illustrates a co-simulation framework to evaluate whole applications compiled for EGRA-accelerated systems, taking into account the impact of non-kernel code and reconfiguration overhead. Success of an architecture paradigm strongly depends on the availability of automated strategies to map applications onto it. The thesis tackles mapping issues at two levels: it proposes a recursive algorithm to partition kernels according to available hardware resources, and it presents a novel modulo scheduling framework, which considers combinatorial chains of computation and routing operations. The thesis touches the areas of architectural exploration, automated kernel mapping and system integration of CGRAs, providing a quantitative analysis of the efficiency of proposed methods over State of the Art ones. It also outlines a comprehensive hardware/software coexploration framewok, able to investigate opportunities and pitfalls of coarse grained reconfiguration. application/pdf https://localhost:5000/ark:/12658/srd1318222 https://susi.usi.ch/global/documents/318222 https://susi.usi.ch/documents/318222/files/2011INFO006.pdf eng info:eu-repo/semantics/altIdentifier/urn/urn:nbn:ch:rero-006-110364 info:eu-repo/semantics/altIdentifier/ark/12658/srd1318222 info:eu-repo/semantics/openAccess License undefined Reconfigurable architectures Coarse grained reconfigurable arrays Hardware/Software co-design Modulo scheduling info:eu-repo/classification/udc/004 Architectural exploration and scheduling methods for coarse grained reconfigurable arrays http://purl.org/coar/resource_type/c_db06